R74 had some bugs and issues related to the new packaging and now the worst is fixed. But that’s not really all that interesting. Instead let’s talk about what manifests and plugin loading changes in R75 can do for you. R74 already introduced recursive loading of all plugins in a directory. This meant that a multi-file plugin like znedi3 could have both its DLL and its data file as a neat group in a separate directory since they belong together.

R75 added manifests, these files are useful if your plugin consist of several support libraries (DLLs) because then VapourSynth can skip wasting time loading the unrelated DLLs. When a manifest file is encountered in a subdirectory only the filenames listed will be loaded and and everything else skipped.

[VapourSynth Manifest V1]
bestsource

The platform specific library ending (.dll/.so/.dylib) is appended to the listed filenames. Multiple filenames with one on each line is allowed. It’s also possible to use relative paths as long as they point to subdirectories.

The other new feature is that a plugin now can have multiple versions compiled for different CPU instruction set levels and automatically load the optimal one for the current system. The levels chosen are:

Level	GCC/Clang	MSVC	Filename
Plain x64 (x86_64_v1)			base.dll
AVX2 level (Intel Haswell, x86_64_v3)	-march=haswell	/arch:AVX2	base.avx2.dll
Zen4 level without AMD only instructions	-march=znver4 -mno-sse4a	No equivalent	base.zn4.dll

If you’re familiar with the defined x86_64 “levels” you may wonder where v2 and v4 went. The short answer is that v2 is mostly pointless (SSE4.2-ish) due to AVX2 (v3) CPUs being so widely available. Intel’s Haswell CPUs were released in 2013.

For v4 the answer is a lot more convoluted because Intel had no plan and no idea about what they were doing. Basically it’s the instruction set of an Intel Skylake CPU with AVX512 enabled. The first consumer CPU with AVX512. And also almost last. Many of the following CPUs from Intel had AVX512 disabled and only enabled for sever parts which nobody actually has at home. This combined with crippling downclocking issues when AVX512 instructions were used means that ironically when you tell most modern compilers to make code for Skylake CPUs (-march=skylake or -march=x86_64_v4) they won’t actually use the wider registers and only use the same register width as AVX2 code. That’s how bad early AVX512 was on consumer CPUs.

Over time more and more AVX512 instructions have also been added that are quite useful. However Intel CPUs would add one new group of instructions and remove another. Meaning that there’s no clear path forward and code compiled for these more modern Intel CPUs wouldn’t necessarily work with later ones. A complete mess. It wasn’t until AMD introduced reasonably priced AVX512 support for consumers with Zen4 things started to fall into place for normal people. At this point, 7 years after the original Skylake, many additional AVX512 instructions had been added. Not only that, Zen5 is a proper superset so it’s fully compatible with Zen4. And so will Zen6 also be. Meaning that from now there’s a consistent target with full width AVX512 used that NORMAL PEOPLE CAN ACTUALLY BUY! This also fits very well with Intel’s coming CPUs with AVX10.2 support that adds very few new instructions of value.